Thesis Archive
Experimental Modules on Integrated Circuit Design Using Tanner for 0.25um, 0.35um, and 0.5um CMOS Process (2011)
ESG-01-1011-05
Jan Romark G. Santiago, Nivas P. Kumar, Ron Alvin V. Escaño and Bour’bon S. Katigbak, advised by Roderick Y. Yap
Abstract:
-The purpose of this study was to make an Experimental Modules on Integrated Circuit Design Using Tanner for 0.35um, 0.25um, and 0.5um CMOS Process. The study includes the development of the environment library for the 0.25um, 0.35um, and 0.5um CMOS processes and the construction, layout designing, DRC, LVS, Parasitic Extraction, and simulation of the circuits. The study also focuses the development of tutorial manuals for using the different designing tools of Tanner EDA, namely L-Edit and S-Edit, in 0.25um, 0.35um, and 0.5um CMOS Processes designing environment.
Correspondence:
Roderick Y. Yap
[email protected]