Analog Realization of a Low-Voltage Sixteen Selectable Fractional-Order Differentiator in a 0.35um CMOS Technology
Authors: Geoffrey L. Abulencia and Alexander C. Abad
Abstract
This paper presents the design and implementation of an analog fractional-order differentiator (FOD) in a microelectronics scale. It focused on the design and implementation of sixteen selectable fractional-order (0.10, 0.20, 0.25, 0.30, 0.35, 0.40, 0.45, 0.50, 0.55, 0.60, 0.65, 0.70, 0.75, 0.80, 0.85 and 0.90) differentiators in a 0.35um CMOS technology operated at 1.5-V supply. In comparison with the previous work that uses generic microcontroller for switching an FOD from one order to the next, this design of a 16 selectable FOD was realized in an analog microelectronic scale, thus, the physical implementation is relatively smaller. The authors employed reusability of resistors and capacitors when switching from one order to the other. The RC ladder in the design was implanted using NMOS capacitor and NWELL resistors while the IC design was implemented using TANNER software. The whole chip layout of the design has a dimension of 11.55mm x 8.32mm or equivalent to a final area of 96.10mm2. Each fractional order was characterized in terms of its frequency response —magnitude and phase response—in the bandwidth from 10Hz to 1kHz.