Thesis Archive

Design and Implementation of a 1 Volt Low Dropout Voltage Regulator on a 0.18 umm CMOS process driving a Clock Circuit Load (2013)

ESG-01-1213-15

Lim, Jacqueline Maye Maranan, Jian Ramark So, Austin

Abstract:

-The main purpose of this research is to design a low dropout voltage regulator (LDO) on 0.18μm CMOS process with a maximum dropout of 500mV at a maximum load current of 500uA current. The specifications of this block are based on its application to regulate the clock circuit of a smart wire chip, which serves as the load. The clock circuit load mentioned above ranges from 100KHz to 7.2MHz. The main component of this block is a folded cascode amplifier that functions as an error amplifier with a PMOS pass transistor that operates mainly at its linear region to function as a resistive device. The error amplifier with a reference value of 0.8V that outputs a specific value to drive the gate of the pass transistor to produce a specific resistance value between the drain and the source to correct the output voltage value to 1V not exceeding the allowable ripple voltage of 100mV given the input voltage of 1.5V with 100mV ripple. The design satisfies the above conditions on all process corners and is implemented using the SYNOPSYS custom designer schematic and layout tool. The circuit has an efficiency of 34.23%, a load regulation of 1.1%, and an accuracy of 97.90% all measured at typical- typical. These parameters are also measured in pre-layout, post-layout on all process corners.

Correspondence:

Ms. Ann Dulay
ann.dulay@dlsu.edu.ph