Thesis Archive

Design and Implementation of an Interleaved Switched Capacitor DC-to-DC Buck Converter on a 0.18 u mm CMOS Process (2013)

ESG-01-1213-03

Lacida, Earl Kenneth Marica, Grace Ann Perocho, Joshua James Tan-Afuan, Karl Ivan Verzosa, Katrina

Abstract:

-DC-DC converters that utilize inductors and capacitors to increase or decrease the voltage level have been replaced with switched capacitor arrays that consist of switches and capacitors. Switched capacitor arrays consume relatively smaller spaces within an integrated circuit while resulting with higher efficiencies. Moreover, this configuration broadens the circuit's bandwidth and also improves system reliability. This research focuses on the design of an interleaved switched capacitor DC-DC buck converter that has an input ranging from 1.4 volts to 1.8 volts, an output a voltage of 1 volt, a maximum output current of 1 milliampere, and a maximum efficiency of 72.266% at an input of 1.4 volts at the SS process corner. The worst load and line regulation of the circuit were characterized as 0.642% and 10.956%, respectively. Also, the design was simulated using a 10 kHz, 1.8 MHz, 3.6 MHz, and 7.2 MHz clock. The biggest transistor used in the circuit has a width of 20 μm and a length of 2.5 μm. There are 32 interleaved switched capacitor arrays whereby each utilizes two clock phases. The proponents implemented the design in the 0.18 micron CMOS technology in the Synopsys tool.

Correspondence:

Ms. Donabel DeVeas
deveasd@dlsu.edu.ph